Andrew Riad

Computer Engineering • Hardware Design

Hi, I’m Andrew Riad.

I’m a junior Computer Engineering student at Cal Poly Pomona focused on computer hardware and digital system design. I’m interested in how hardware components interact at the logic and system level, from design and simulation to testing and verification.

Get in touch View projects Download resume
Location Rancho Cucamonga, CA
Looking for Hardware Engineering Internship
Languages English, Arabic, Spanish (basic)
Headshot photo

About

A quick snapshot of who I am and what I’m aiming for.

I’m a Computer Engineering student with a strong interest in computer hardware and digital system design. I enjoy working at the logic and architecture level—designing, analyzing, and testing hardware systems to understand how individual components interact and perform as a whole.

My approach to engineering emphasizes reasoning from specifications, accounting for constraints, and validating designs through simulation and hands-on testing. I’m particularly drawn to digital logic and hardware behavior.

I’m currently seeking a hardware engineering internship where I can contribute to design and verification work while continuing to build practical experience in computer hardware systems.

Digital Logic Circuit Analysis Embedded Fundamentals Troubleshooting C / C++ / C# CAD / 3D Modeling

Education

Coursework foundations and current track.

California State Polytechnic University, Pomona

B.S. Computer Engineering (Junior Transfer) • Aug 2025 — Jan 2027 (Expected)

GPA: 3.6

Chaffey College — Rancho Cucamonga

Associate’s in Physical Science • Jan 2022 — Aug 2025

Associates degree for Transfer in Physical Science

Associates degree for Transfer in Mathematics

GPA: 3.6

Skills

Tools and strengths I bring to a team.

Engineering

  • Circuit analysis & simulation
  • Breadboard & lab testing
  • Embedded systems basics
  • Hardware troubleshooting
  • Digital systems fundamentals

Software & Tools

  • C / C++ / C#
  • 3D modeling & CAD
  • Microsoft 365
  • QuickBooks
  • Spreadsheet automation (ops + inventory)

How I work

I like structured problem solving: define requirements, build a minimal prototype, test quickly, then iterate. I communicate clearly, document what I change, and keep projects organized.

Experience

Roles that built my operations, communication, and technical troubleshooting skills.

Office Manager

Lock and Roll Locksmith • Feb 2025 — Present

  • Managed daily office operations: scheduling, client communication, and logistics for multiple technicians.
  • Improved accuracy and efficiency by implementing digital tracking systems and better data organization.
  • Oversaw inventory management and supply ordering with spreadsheets and digital recordkeeping.
  • Assisted with hardware/software troubleshooting for office computers, POS, and scheduling platforms.
  • Maintained customer database integrity and service documentation for reliable field communication.

Sales Associate

Office Depot • Oct 2023 — Feb 2025

  • Provided customer service and sales support in a fast-paced retail environment.
  • Advised customers on computers, printers, and tech products by comparing options and recommending solutions.
  • Handled POS transactions, returns, online order fulfillment, and inventory restocking.

Projects

Selected labs and builds (with schematics + breadboard photos).

4×16 Decoder + Minterm Display (74LS138) image 1
4×16 Decoder + Minterm Display (74LS138) image 2
4×16 Decoder + Minterm Display (74LS138) image 3
4×16 Decoder + Minterm Display (74LS138) image 4

4×16 Decoder + Minterm Display (74LS138)

Designed a 4×16 decoder using two 3-to-8 decoders and minimal logic. Generated minterms 1/5/9 and drove a seven-segment display; blanked the display and lit an “OTHER” LED for all other inputs.

DecodersCombinational7‑SegmentTTL
Lab Report (PDF)
5-bit Signed Adder/Subtractor (74LS283 / 74LS86) image 1
5-bit Signed Adder/Subtractor (74LS283 / 74LS86) image 2
5-bit Signed Adder/Subtractor (74LS283 / 74LS86) image 3
5-bit Signed Adder/Subtractor (74LS283 / 74LS86) image 4

5-bit Signed Adder/Subtractor (74LS283 / 74LS86)

Implemented a signed 5-bit adder/subtractor using cascaded full adders with XOR-controlled inversion for two’s-complement subtraction. Added sign + overflow LEDs and displayed results via BCD on a seven-seg.

ArithmeticTwo’s ComplementOverflowBCD
Lab Report (PDF)
EPROM Lookup: Square of a BCD Digit image 1
EPROM Lookup: Square of a BCD Digit image 2
EPROM Lookup: Square of a BCD Digit image 3

EPROM Lookup: Square of a BCD Digit

Built an EPROM-based lookup table that outputs the square of a BCD input and drives two seven-segment displays. Verified correct outputs across 0–9 inputs (with the lab’s group-specific mapping).

MemoryEPROMLookup Table7‑Segment
Lab Report (PDF)
Nonbinary Sequence Counter (0,1,2,4,5,6,7) image 1
Nonbinary Sequence Counter (0,1,2,4,5,6,7) image 2
Nonbinary Sequence Counter (0,1,2,4,5,6,7) image 3

Nonbinary Sequence Counter (0,1,2,4,5,6,7)

Designed and built a nonbinary counter using T flip-flops (implemented with JK FFs). Derived logic with state table/K-maps and verified the sequence on a seven-seg display, including self-correction behavior.

CountersSequential LogicK‑MapsVerification
Lab Report (PDF)
4-bit General-Purpose Register image 1
4-bit General-Purpose Register image 2
4-bit General-Purpose Register image 3

4-bit General-Purpose Register

Created a 4-bit register supporting parallel load, rotate-left, rotate-right, and increment operations using multiplexers and flip-flops. Demonstrated each mode on LEDs with switch-controlled selects.

RegistersMUXControl LogicAdders
Lab Report (PDF)

Contact

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